As CMOS technology is scaled into the deep sub-100 nm regime, random variability of important device parameters is becoming of increasing concern. Variation of threshold voltage (Vt) of small static random access memory (SRAM) field effect transistors (FETs) is a prime example of such a concern since at the 45 nm technology node the standard deviation can exceed 50 mV. Metal to silicon contacts provide another example in which the mean and the variance of the contact resistance R(CA) are both becoming significant on the scale of the switching resistance of representative logic gates. Both the mean values and variances of important technology parameters must be characterized on a regular basis throughout the life cycle of a technology. The most straightforward way of accomplishing such characterizations is to measure a large enough number of nominally identical test structures to obtain mean values and variances to an adequate level of confidence.
Using FET characterization as an example, there are presently two common approaches for acquiring data on large numbers of FETs. The first is a brute force, single metal level (M1), approach in which, for example, 14-20 FETs are wired up in a single minimum sized 1×25 padset macro, which is then repeated multiple times. This approach is extremely inefficient from a real estate perspective. Further, the spatial extent of the collection of FETs is several millimeters, and care must be taken to subtract out any spatial variations that may be convolved with the statistical variations under study. Advantageously, in this approach the FETs can be unambiguously and individually measured and characterized with no voltage or current corrections required.
The second approach utilizes a large addressable array, typically measurable at fourth metal level (M4) or above. See, for example, T. Mizuno et al., “Experimental Study of Threshold Voltage Fluctuations Using an 8 k MOSFET Array,” Symp. VLSI Tech. Digest, p. 41 (1993); U. Schaper et al., Parameter Variation on Chip Level,” Proceedings of the IEEE International Conference on Microelectronics Test Structures, pp. 155-158 (2005); and K. Agarwal et al., “A Test Structure for Characterizing Local Device Mismatches,” Symp. VLSI Tech., pp. 82-83 (2006). There may be several tens of thousands of FETs or more in a single macro. These designs are often single port, although multiport versions also exist. Test times tend to be long and voltage drop corrections due to series resistance and current corrections due to parallel leakage paths must be carefully made and ultimately limit the accuracy of the measurements and/or the range of current/voltage (IV) space over which accurate measurements can be made.
Wiring up an addressable array typically requires many low to moderately low resistance wiring tracks in both X and Y directions. An entire test chip of approximately 32 mm×25 mm in size has been demonstrated, using only M1, with such arrays in a two dimensional configuration (of order 100), where each array contained about 300 devices under test (DUTs). See K. Y. Doong et al., “Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model and Manufacturability,” Proceedings of the IEEE International Conference on Microelectronics Tests Structures, pp. 98-103 (2006). Crossovers are wired with relatively high resistance silicided polysilicon (PC) or diffusion (RX) areas. A large area for this design was required to wire everything up in an acceptably low resistance fashion and the arrays were not of a form factor that would allow easy placement in the scribe line (kerf) of a product chip.